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SYNC PULSE
V SYNC_COMP
SYNC_LPF_RESET
SYNC OFF
SYNC_PULSE_PD
RESPONSE
t A_SYNC_DLY
t PD_DLY
t PD_ON
t SYNC_LPF_RST_ST
t TRIG
t SYNC_LPF_RST
t SYNC_OFF_xxx
t TIMESLOTx
Figure 28. Synchronization Pulse Detection Timing
4.2.1.2
Synchronization Pulse Pulldown Function
The device includes an optional Sync pulse pulldown function for systems in which the master device does not include an
active pulldown function. The modulation current pulldown circuit is used, which sinks I MOD -I IDLE additional current from the I DATA
pin. The pulldown current is activated after t PD_DLY (referenced to t TRIG), and is activated for t PD_ON .
4.3
4.3.1
Data Transmission Data Link Layer
Bit Encoding
The device outputs data by modulation of the V CC current using Manchester 2 Encoding. Data is stored in a transition occurring
in the middle of the bit time. The signal idles at the normal quiescent supply current. A logic low is defined as an increase in
current at the middle of a bit time. A logic high is defined as a decrease in current at the middle of a bit time. There is always a
transition in the middle of the bit time. If consecutive “1” or “0” data are transmitted, There will also be a transition at the start of
a bit time.
I MOD CURRENT
IDLE CURRENT
‘ 0’ BIT
t BIT
‘1’ BIT
SENSED HIGH
SENSED LOW
CONSECUTIVE
‘0’ DATA BITS
CONSECUTIVE
‘1’ DATA BITS
Figure 29. Manchester 2 Data Bit Encoding
MMA52xxKW
Sensors
Freescale Semiconductor, Inc.
35
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